1. Field of the Invention
The present invention is related to an electrostatic discharge (ESD) protection circuit. In particular, the present invention relates to an ESD protection circuit for differential pairs.
2. Description of the Prior Art
ESD is one of the most important reliability issues for integrated circuit (IC) products and must be taken into consideration during the design phase of all ICs. ESD events can be classified in to several modes: PS-mode, ND-mode, PD-mode, NS-mode, and pin-to-pin mode.
Under positive-to-VSS (PS-mode) ESD stresses, a positive ESD zapping is applied to an input pad while the VSS power rail is grounded and the VDD power rail is floating. Under negative-to-VDD (ND-mode) ESD stresses, a negative ESD zapping is applied to an input pad while the VDD power rail is grounded and the VSS power rail is floating. Under positive-to-VDD (PD-mode) ESD stresses, a positive ESD zapping is applied to an input pad while the VDD power rail is grounded and the VSS power rail is floating. Under negative-to-VSS (NS-mode) ESD stresses, a negative ESD zapping is applied to an input pad while the VSS power rail is grounded and the VDD power rail is floating.
Recently, more and more high-speed communication circuits and radio-frequency (RF) frond-end circuits are realized with differential input/output stages because differential configuration can suppress impacts caused by common-mode interferences. However, differential I/O pairs are especially susceptible to pin-to-pin ESD attacks. In a pin-to-pin ESD event, ESD voltage is stressed on one pin of the differential I/O pair while the other pin is grounded. If the ESD voltage across the differential pair cannot be eliminated effectively, the device undertaken the ESD voltage (e.g. gate of a MOSFET) will be damaged.
FIG. 1 shows an ESD protection circuit for differential I/O pairs disclosed in “ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications” reported by M.-D. Ker, T.-Y. Chen, C.-Y. Wu, and H.-H. Chang on IEEE J. Solid-State Circuits, vol. 35, no. 8, pp. 1194-1199, August 2000. This protection circuit includes gate-VDD PMOSs (Mp1, Mp2), gate-grounded NMOSs (Mn1, Mn2), and a power-rail ESD clamp circuit 10.
As shown in FIG. 1, a differential input stage 12 is respectively connected to a first input pad 14 and a second input pad 16. Once an ESD voltage is stressed on the first input pad 14 while the second input pad 16 is grounded, ESD currents will flow to ground through the PMOS Mp1, power-rail ESD clamp device 10 (from VDD to VSS), NMOS Mn2, and finally to the second input pad 16.
The ESD protection configuration in the above prior art has a disadvantage. Because the ESD clamp circuit 10 is typically located far from the differential input stage 12 in actual layout, the parasitic resistance on metal lines between the ESD clamp circuit 10 and the differential input stage 12 might not be small. Since ESD currents are generally large, the cross voltage induced by the parasitic resistance cannot be ignored. In other words, the ESD voltage across the I/O pairs of the differential input stage 12 still might damage the input components.
FIG. 2 illustrates another traditional ESD protection circuit for differential I/O pairs. In this configuration, each input pad (24, 26) of the differential input stage 22 is coupled with two diodes (D1˜D4); one diode is connected between VDD and the input pad, and the other diode is connected between the input pad and VSS. Once an ESD voltage is stressed on the first input pad 24 while the second input pad 26 is grounded, ESD currents will flow to ground through the diode D1, power-rail ESD clamp device 20 (from VDD to VSS), diode D4, and finally to the second input pad 26. Similarly, the ESD clamp circuit 20 is generally located far from the differential input stage 22, and large parasitic resistance between them may also induce the problem above.
To solve the aforementioned problem, clamp devices configured more directly between two inputs of the differential pair is utilized. FIG. 3 illustrates an ESD protection circuit disclosed in the U.S. Pat. No. 6,507,471. The differential input stage includes two input devices (Q1, Q2) and three resistors (RE, RL1, RL2). As shown in FIG. 3, an NMOS Q3 is connected between the differential input pads (34, 36).
Diodes D1˜D4 and a power-rail ESD clamp circuit 30 are used to protect the differential pair (34, 36) against PS-mode, PD-mode, NS-mode, and ND-mode ESD stresses. Under pin-to-pin ESD stresses, one differential input pad is zapped by ESD while the other differential input pad is relatively grounded. When a pin-to-pin ESD occurs, the NMOS Q3 will be turned on to provide ESD current path between the differential input pads.
FIG. 4 illustrates another ESD protection circuit disclosed in the U.S. Pat. No. 6,693,780. In this configuration, four diodes (D5˜D8) are connected between the differential input pads (44, 46) to provide ESD current path under pin-to-pin ESD stresses. Besides, diodes D9 and D10 are applied to provide ESD protection against pin-to-pin ESD stresses. When input pad 44 is zapped by ESD with input pad 46 grounded, the diodes D5 and D6 will be forward biased to bypass ESD currents. Moreover, the base-emitter junction of Q1 and diode D10 can provide another ESD current path to protect the differential pair against pin-to-pin ESD stresses.